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[Other resource] jtag

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 636270 | Author: hegs | Hits:

[Other resource] BiDirectionalCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 1027 | Author: hegs | Hits:

[Other resource] ControlCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 1338 | Author: hegs | Hits:

[Other resource] InputCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 1192 | Author: hegs | Hits:

[Other resource] OutputCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 1416 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] fir

Description: 完成一个FIR数字滤波器的设计。要求： 1、 基于直接型和分布式两种算法。 2、 输入数据宽度为8位，输出数据宽度为16位。 3、 滤波器的阶数为16阶，抽头系数分别为h[0]=h[15]=0000，h[1]=h[14]=0065，h[2]=h[13]=018F，h[3]=h[12]=035A，h[4]=h[11]=0579，h[5]=h[10]=078E，h[6]=h[9]=0935，h[7]=h[8]=0A1F。 -Completion of a FIR digital filter design. Requirements: one, based on the direct type and distributed two algorithms. 2, input data width of 8, the output data width of 16. 3, filter order of 16 bands, tap coefficients for h [0] = h [15] = 0000, h [1] = h [14] = 0065, h [2] = h [13] = 018F , h [3] = h [12] = 035A, h [4] = h [11] = 0579, h [5] = h [10] = 078E, h [6] = h [9] = 0935, h [7] = h [8] = 0A1F.
Platform: | Size: 5120 | Author: fredyu | Hits:

[VHDL-FPGA-Verilog] jtag

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 635904 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] BiDirectionalCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 1024 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] ControlCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 1024 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] OutputCell

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
Platform: | Size: 1024 | Author: hegs | Hits:

[Other] JTAG-TAP

Description: JTAG TAP controller verilog source code
Platform: | Size: 5120 | Author: kdlee | Hits:

[Other] c73a2ceb-09a5-4366-83ea-78b08c6200eb

Description: jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
Platform: | Size: 2048 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
Platform: | Size: 352256 | Author: hongwan | Hits:

[source in ebook] IIR_Filter_8

Description: verilog实现8阶的iir滤波器。对于刚学习verilog的朋友来说是一个易懂的学习资料。-verilog order to achieve the iir filter 8. For just learning verilog friend is a easy to understand learning materials.
Platform: | Size: 1024 | Author: zh | Hits:

[VHDL-FPGA-Verilog] TAP1

Description: JTAG TAP statemachine verilog code
Platform: | Size: 1024 | Author: 张超 | Hits:

[VHDL-FPGA-Verilog] TAP2

Description: JTAG TAP Statemachine verilog code
Platform: | Size: 1024 | Author: 张超 | Hits:

[VHDL-FPGA-Verilog] TAP4

Description: JTAG TAP Statemachine verilog code
Platform: | Size: 1024 | Author: 张超 | Hits:

[VHDL-FPGA-Verilog] matlab-and-verilog-fir4_3

Description: 四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
Platform: | Size: 8192 | Author: 李静 | Hits:

[VHDL-FPGA-Verilog] JTAG_Example0_Verilog

Description: 一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))
Platform: | Size: 386048 | Author: ZhouGuofei | Hits:

[Other] tap_controller

Description: JTAG tap controller, used for DFT(JTAG tap controller verilog version)
Platform: | Size: 1024 | Author: borselin | Hits:
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